1. Field of the Invention
The present invention relates to a pipeline A/D converter that performs A/D conversion using a plurality of operational stages that are connected in series and to a method of performing pipeline A/D conversion.
2. Description of Related Art
As digitization proceeds in the fields of audiovisual and telecommunication, it has been required for A/D converters used as key devices in these fields to achieve higher speed and higher resolution.
FIG. 7 is a block diagram showing the configuration of a generally used pipeline A/D converter. This pipeline A/D converter includes a sample hold circuit 1 to which an analog input signal Ain is input and (N−1) stages (a first stage 2[1] to an (N−1)th stage 2[N−1]) connected in series with the sample hold circuit 1. In the following description, the stages 2[1] to 2[N−1] may be referred to generically as “stages 2[k]”, where k denotes an integer from 1 to (N−1).
The sample hold circuit 1 and the stages 2[k] output digital signals D1 to DN, respectively, to supply them to a digital computing circuit 3. The digital computing circuit 3 outputs an N-bit A/D converted output signal Dout based on the digital signals D1 to DN. The number (N−1) of the stages 2[k] connected in series varies depending on the resolution of the A/D converter.
The sample hold circuit 1 includes a sample hold portion that samples and holds the analog input signal Ain and a ternary coding circuit. The sample hold amplifier (SHA) circuit 1 determines a digital signal D1 as ternary data based on a voltage Vo(1) that has been sampled and held by the sample hold portion, and outputs the digital signal D1 to the digital computing circuit 3. The digital signal D1 also is supplied to the first stage 2[1] at the same time. To the first stage 2[1], the voltage Vo(1) is supplied as an analog output signal. In the first stage 2[1], a digital signal D2 and an analog output signal Vo(2) are generated based on the digital signal D1 and the analog output signal Vo(1), and the thus-generated digital signal D2 and analog output signal Vo(2) are output to the digital computing circuit 3 and the second stage 2[2]. Similarly, in the kth stage 2[k], a digital signal Dk and an analog output signal Vo(k) are generated based on a digital signal D(k−1) and an analog output signal Vo(k−1), and the thus-generated digital signal Dk and analog output signal Vo(k) are output to a subsequent (k+1)th stage 2[k+1].
The stage 2[k] has a configuration as shown in FIG. 8, and includes a ternary coding circuit 4, an analog reference signal generation circuit 5, and an analog signal processing circuit 6. It is to be noted here that, for the sake of convenience in illustration, FIG. 8 shows the ternary coding circuit 4 that belongs to a preceding (k−1)th stage 2[k−1]. Thus, an analog output signal Vo(k−1) of the (k−1)th stage 2[k−1] is input to the ternary coding circuit 4, and the ternary coding circuit 4 outputs a digital signal D(k−1) based on this analog output signal Vo(k−1).
The digital signal D(k−1) output from the ternary coding circuit 4 is input to the analog reference signal generation circuit 5 of the kth stage 2[k]. The analog reference signal generation circuit 5 outputs an analog reference signal +Vref, −Vref, or 0V depending on the digital signal D(k−1) and supplies it to the analog signal processing circuit 6. The analog output signal Vo(k−1) from the preceding stage further is input to the analog signal processing circuit 6, and the analog signal processing circuit 6 performs an amplifying operation by adding the analog output signal Vo(k−1) and the analog reference signal.
The analog signal processing circuit 6 is a switched-capacitor type amplifier using capacitors. The analog signal processing circuit 6 includes an operational amplifier 7, capacitors C1 and C2 (hereinafter, the capacitances of the capacitors C1 and C2 also are denoted with C1 and C2, respectively), and switches SW1, SW2, SW3, SW4, and SW5. The switches SW1, SW2, and SW5 are turned ON/OFF according to a clock timing Φ1 shown in FIG. 9. On the other hand, the switches SW3 and SW4 are turned ON/OFF according to a clock timing Φ2.
Next, an operation of the analog signal processing circuit 6 in FIG. 8 will be described. In the clock timing shown in FIG. 9, T represents a period in which a single A/D conversion is performed. The period T includes a period A and a period B. In the period A of the clock timing, the switches SW1, SW2, and SW5 shown in FIG. 8 are turned ON while the switches SW3 and SW4 are turned OFF, so that electric charges of the analog output signal Vo(k−1) from the preceding stage are sampled by the capacitors C1 and C2. In the period B of the clock timing, the switches SW3 and SW4 shown in FIG. 8 are turned ON while the switches SW1, SW2, and SW5 are turned OFF. Thus, the electric charges that have been sampled by the capacitors C1 and C2 in the period A are reallocated, so that, in accordance with the principle of conservation of charge, an analog output signal Vo(k) with a value corresponding to (C1+C2)/C2 times the voltage obtained by adding/subtracting the analog reference signal to/from the analog output signal Vo(k−1) is output from the operational amplifier 7.
The analog signal processing circuit 6 in each of the stages operates in the above-described manner. The pipeline A/D converter with the above-described configuration as a whole operates in such a manner that, for example, the sample hold circuit 1 and the even-numbered stages perform the sampling operation in the period A of the clock timing shown in FIG. 9 and perform the amplification by a factor of (C1+C2)/C2 and the output in the period B, while the odd-numbered stages perform the sampling operation in the period B shown in FIG. 9 and perform the amplification by a factor of (C1+C2)/C2 and the output in the period A.
As also described in “IEEE J. SOLID-STATE CIRCUITS, Vol. 36, pp. 1931-1936, December 2001, ‘A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR’”, the relative accuracy of capacitors constituting an operational amplifier determines the resolution of an A/D converter. It has been known that a capacitor with a larger capacitance generally achieves a higher relative accuracy and the capacitance conforming to the desired resolution needs to be set based on the relative accuracy of the capacitor.
However, in the case of an A/D converter of more than 14 bits, capacitors used therein are required to achieve a very high relative accuracy. This is because errors in the respective stages accumulate to be amplified due to an error in relative accuracy of the capacitor in each of the stages, so that the effect thereof becomes nonnegligible in the end. In order to eliminate the influence of the error accumulation caused by the relative accuracy of the capacitor, JP 2001-352244 A discloses the configuration of each stage as shown in FIGS. 10 to 12.
A ternary coding circuit 4 and an analog reference signal generation circuit 5 shown in FIG. 10 have the same configurations as those in FIG. 8. However, the configuration of an analog signal processing circuit 6a is different from that shown in FIG. 8, and switches SW6 to SW12 are provided for an operational amplifier 7 and capacitors C1 and C2. The switches SW6, SW7, and SW12 are turned ON/OFF according to a clock timing Φ11 shown in FIG. 11. The switches SW9 and 10 are turned ON/OFF according to a clock timing Φ21. The switches SW8 and SW11 are turned ON/OFF according to a clock timing Φ22.
With this configuration, the analog signal processing circuit 6a performs, in periods T1 and T2 obtained by dividing a period T of the clock timing shown in FIG. 11 into two equal periods, a sampling and holding operation twice on a time-division basis according to the clock timing Φ11. The analog signal processing circuit 6a outputs an analog output signal Vo(k) in each of the sampling and holding operations. That is, in each of the first period T1 and the second period T2 in FIG. 11, an analog output signal from the preceding stage is sampled by the first and second capacitors, and thereafter, either one of these capacitors is used as a feedback element of the operational amplifier 7 and the operational amplifier 7 performs addition/subtraction of a predetermined analog reference signal output from the analog reference signal generation circuit 5 to/from the analog output signal that has been sampled by the other capacitor.
Furthermore, based on an analog output signal Vo(k−1) from the preceding stage, the ternary coding circuit 4 performs ternary coding in each of the period T1 and the period T2 shown in FIG. 11. Then, as shown in FIG. 12, the configuration of the operational amplifier 7 included in each of the stages is switched depending on its logic state. With this configuration, it is possible to minimize the error caused by the relative accuracy of the capacitors.
More specifically, in the period T1, the first capacitor is used as a feedback element when the output from the ternary coding circuit 4 is in a first logic state, and the second capacitor is used as a feedback element when the output from the ternary coding circuit 4 is in a second logic state. On the other hand, in the period T2, the second capacitor is used as a feedback element when the output from the ternary coding circuit 4 is in the first logic state, and the first capacitor is used as a feedback element when the output from the ternary coding circuit 4 is in the second logic state. Furthermore, the outputs obtained in the periods T1 and T2 that have been coded into ternary data by the ternary coding circuit 4 in each of the stages are averaged by an averaging circuit. This allows the integrated error to be minimized, thus realizing a high-resolution A/D converter.
However, with the above-described conventional configuration, the operations in the first period T1 and the second period T2 are performed within the operation period of the A/D converter (the period T in FIG. 11). Thus, when the A/D converter is operated at a high speed, the operational amplifier and the ternary coding circuit included in each of the stages need to achieve a very high operation speed. Therefore, it is very difficult to realize a high-resolution and high-speed A/D converter.